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publication number s29al008d_00 revision a amendment 11 issue date february 27, 2009 s29al008d s29al008d cover sheet 8 megabit (1m x 8-bi t/512 k x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet this product has been retired and is not recommended for designs. for new and current designs, s29al008j supercedes s29al008d. this is the factor y-recommended migration path. please refer to the s29al008j data sheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only. notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29al008d s29al008d_00_a11 february 27, 2009 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
publication number s29al008d_00 revision a amendment 11 issue date february 27, 2009 this product has been retired and is not recommended for de signs. for new and current designs, s29al008j supercedes s29al008d. this is the factory-recommended migration path. please refer to the s29al008j data sheet for specifications and ordering information. distinctive characteristics architectural advantage ? single power supply operation ? 2.7 to 3.6 volt read and write operations for battery-powered applications ? manufactured on 200 nm process technology ? compatible with 0.32 m and 230 nm am29lv800 devices ? flexible sector architecture ? one 16-kbyte, two 8-kbyte, one 32-kbyte, and fifteen 64-kbyte sectors (byte mode) ? one 8 kword, two 4 kword, one 16-kword, and fifteen 32-kword sectors (word mode) ? supports full chip erase ? sector protection features: ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? top or bottom boot block configurations available ? embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses ? compatibility with jedec standards ? pinout and software compatible with single-power supply flash ? superior inadvertent write protection performance characteristics ? high performance ? access times as fast as 55 ns ? extended temperature range (-40c to +125c) ? ultra-low power consumption (typical values at 5 mhz) ? 200 na automatic sleep mode current ? 200 na standby mode current ? 7 ma read current ? 15 ma program/erase current ? cycling endurance: 1,000,000 cycles per sector typical ? data retention: 20 years typical ? reliable operation for the life of the system package option ? 48-ball fbga ? 48-pin tsop ? 44-pin so software features ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion ? erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data s29al008d 8 megabit (1m x 8-bi t/512 k x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet
4 s29al008d s29al008d_00_a11 february 27, 2009 data sheet general description the s29al008d is an 8 mbit, 3.0 volt-only flash memory organized as 1,048,576 bytes or 524,288 words. the device is offered in 48-ball fbga, 44-pin so, and 48-pin tsop packages. for more information, refer to publication number 21536. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. this device requ ires only a single, 3.0 volt v cc supply to perform read, program, and erase operations. a standard eprom programmer can al so be used to program and erase the device. this device is manufactured using spansion?s 200 nm process technology, and offers all the features and benefits of the am29lv 800b, which was manufactured us ing 0.32 m process technology. the standard device offers access times of 55, 60, 70, and 90 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus conten tion the device contains separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provi ded for the program and erase operations. the device is entirely command set compatible with the jedec single-power-s upply flash standard . commands are written to the command register usin g standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data n eeded for the programming and erase operations. reading data out of the device is similar to re ading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that automati cally times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program dat a instead of four. device erasure occurs by executing the er ase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically prepr ograms the array (if it is not already programmed) before executing the erase op eration. during erase, the device au tomatically times the erase pulse widths and verifies proper cell margin. the host system can detect wh ether a program or erase operation is co mplete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle is completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of t he sectors of memory. this can be ac hieved in-system or via programming equipment. the erase suspend feature enables the user to put erase on hold fo r any period of time to read data from, or program data to, any sector that is not selected fo r erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitr y. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when addresse s are stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. spansion?s flash technology combines years of flas h memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electric ally erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
february 27, 2009 s29al008d_00_a11 s29al008d 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 special handling instructions for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 program and erase operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 7.8 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.11 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4 word/byte program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 unlock bypass command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 9.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1 zero power flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 14. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15.1 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15.2 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 16. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 16.1 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.2 vbk 048?48 ball fine-pitch ball gr id array (fbga) 8.15 x 6.15 mm . . . . . . . . . . . . . . . . . 47 16.3 so 044?44-pin small outline package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 17. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.1 revision a (september 8, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.2 revision a 1 (february 18, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.3 revision a2 (june 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.4 revision a3 (june 16, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.5 revision a4 (february 16, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.6 revision a5 (may 22, 2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.7 revision a6 (september 6, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.8 revision a7 (october 31, 2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.9 revision a8 (august 29, 2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.10 revision a9 (september 19, 2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.11 revision a10 (november 27, 2007). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 17.12 revision a11 (february 18, 2009) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
february 27, 2009 s29al008d_00_a11 s29al008d 7 data sheet figures figure 3.1 standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.2 so pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.3 fine-pitch bga pi nout (top view, balls facing down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7.1 temporary sector unprotect operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7.2 in-system sector protect/sector unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9.2 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12.1 i cc1 current vs. time (showing active and automatic s leep currents) . . . . . . . . . . . . . . . . 34 figure 12.2 typical i cc1 vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14.1 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15.1 read operations timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15.2 reset# timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15.3 byte# timings for read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15.4 byte# timings for write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15.5 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15.6 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15.7 back to back read/write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15.8 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15.9 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15.10 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15.11 temporary sector unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15.12 sector protect/unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15.13 alternate ce# controlled write operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8 s29al008d s29al008d_00_a11 february 27, 2009 data sheet tables table 7.1 s29al008d device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7.2 s29al008d top boot block sector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7.3 s29al008d bottom boot block sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.4 s29al008d autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8.1 s29al008d command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9.1 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15.3 word/byte configuration (byte#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15.4 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15.5 alternate ce# controlled erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15.6 latchup characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 15.7 tsop, so, and bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
february 27, 2009 s29al008d_00_a11 s29al008d 9 data sheet 1. product selector guide note see ac characteristics on page 36 for full specifications. 2. block diagram family part number s29al008d speed options full voltage range: v cc = 2.7 ? 3.6 v 60 70 90 regulated voltage range: v cc = 3.0 ? 3.6v 55 max access time, ns (t acc ) 55607090 max ce# access time, ns (t ce ) 55607090 max oe# access time, ns (t oe ) 25253035 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a18
10 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 3. connection diagrams figure 3.1 standard tsop figure 3.2 so pinout a1 a15 a18 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# a17 a7 a6 a5 a4 a3 a2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 reset# we# a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc
february 27, 2009 s29al008d_00_a11 s29al008d 11 data sheet figure 3.3 fine-pitch bga pinout (top view, balls facing down) 3.1 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cl eaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 nc nc reset# we# dq11 dq3 dq10 dq2 nc a18 nc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3
12 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 4. pin configuration 5. logic symbol i/o name description a0?a18 19 addresses dq0?dq14 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) byte# selects 8-bit or 16-bit mode ce# chip enable oe# output enable we# write enable reset# hardware reset pin, active low ry/by# ready/busy# output v cc 3.0 volt-only single power supply (see product selector guide on page 9 for speed options and voltage supply tolerances) v ss device ground nc pin not connected internally 19 16 or 8 dq0?dq15 (a-1) a0?a18 ce# oe# we# reset# byte# ry/by#
february 27, 2009 s29al008d_00_a11 s29al008d 13 data sheet 6. ordering information this product has been retired and is not recommended for designs. for new and current designs, s29al008j supercedes s29al008d. this is the factory-recomme nded migration path. please refer to the s29al008j data sheet for specifications and ordering information. 6.1 standard products spansion standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes 1. type 0 is standard. specify other options as required. 2. type 1 is standard. specify other options as required. 3. tsop and sop package markings omit packing type designator from ordering part number. 4. bga package marking omits leading s29 and packing type designator from ordering part number. s29al008d 55 t a i ri 0 packing type 0=tray 1 = tube 2 = 7? tape and reel 3 = 13? tape and reel model number 01 = x8/x16, v cc = 2.7 - 3.6v, top boot sector device r1 = x8/x16, v cc = 3.0 - 3.6v. top boot sector device 02 = x8/x16, v cc = 2.7 - 3.6v, bottom boot sector device r2 = x8/x16, v cc = 3.0 - 3.6v. bottom boot sector device temperature range i = industrial (-40c to +85c) n = extended (-40c to +125c) package material set a = standard f = pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package m = small outline package (sop) standard pinout speed option 55 = 55 ns access speed 60 = 60 ns access speed 70 = 70 ns access speed 90 = 90 ns access speed device number/description s29al008d 8 megabit flash memory manufactur ed using 200 nm process technology 3.0 volt-only read, program, and erase s29al008d valid combinations package description device number speed option package type, material, and temperature range model number packing type s29al008d 55 tai, tfi r1, r2 0, 3 (note 1) ts048 (note 3) tsop 60, 70, 90 tai, tfi, tan, tfn 01, 02 55 bai, bfi r1, r2 0, 2, 3 (note 1) vbk048 (note 4) fine-pitch bga 60, 70, 90 bai, bfi, ban, bfn 01, 02 55 mai, mfi r1, r2 0, 1, 3 (note 2) so044 (note 3) sop 60, 70, 90 mai, mfi, man, mfn 01, 02
14 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 7. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is composed of latc hes that store the commands, along with the address and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine output s dictate the function of the device. table 7.1 lists the device bus operations, the inputs and control levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. legend l = logic low = v il h = logic high = v ih v id = 12.0 0.5 v x = don?t care a in = address in d in = data in d out = data out notes 1. addresses are a18:a0 in word mode (byte# = v ih ), a18:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see sector protection/ unprotection on page 18 . 7.1 word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configuration. if the byte# pin is set at logic 1, the device is in word configur ation, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. 7.2 requirements for reading array data to read array data from the outputs, the syst em must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output cont rol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the de vice outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the de vice remains enabled for read access until the command register contents are altered. table 7.1 s29al008d device bus operations operation ce# oe# we# reset# addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l h a in d in d in standby v cc 0.3 v xx v cc 0.3 v x high-z high-z high-z output disable l h h h x high-z high-z high-z reset x x x l x high-z high-z high-z sector protect (note 2) lhl v id sector address, a6 = l, a1 = h, a0 = l d in xx sector unprotect (note 2) lhl v id sector address, a6 = h, a1 = h, a0 = l d in xx temporary sector unprotect x x x v id a in d in d in high-z
february 27, 2009 s29al008d_00_a11 s29al008d 15 data sheet see reading array data on page 21 for more information. refer to table 15.1, read operations on page 36 for timing specifications and to figure 15.1 on page 36 for the timing diagram. i cc1 in dc characteristics on page 33 represents the active current specification for reading array data. 7.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whet her the device accepts program data in bytes or words. refer to word/byte configuration on page 14 for more information. the device features an unlock bypass mode to facilitate faster programm ing. once the device enters the unlock bypass mode, only tw o write cycles are required to program a word or by te, instead of four. the word/ byte program command sequence on page 22 contains details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table 7.2 on page 16 and table 7.3 on page 17 indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. the command definitions on page 21 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autose lect command sequence, the device en ters the autoselect mode. the system can then read autoselec t codes from the internal register (whi ch is separate from the memory array) on dq7?dq0. standard read cycle timings apply in th is mode. refer to the autoselect mode on page 18 and autoselect command sequence on page 22 for more information. i cc2 in dc characteristics on page 33 represents the active current specification for the write mode. the ac characteristics on page 36 contains timing specification tables and timing diagrams for write operations. 7.4 program and erase operation status during an erase or program operatio n, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to write operation status on page 27 for more information, and to ac characteristics on page 36 for timing diagrams. 7.5 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device is in the standby mode, but t he standby current is grea ter. the device requires standard access time (t ce ) for read access when the device is in eith er of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. in dc characteristics on page 33 , i cc3 and i cc4 represents the standby current specification. 7.6 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 in dc characteristics on page 33 represents the automatic sleep mode current specification.
16 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 7.7 reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read /write commands for the durat ion of the reset# pulse. the device also resets the internal state machine to reading array data. the oper ation that was interrupted should be reinitiated once the device is ready to acc ept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or er ase operation, the ry /by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase operat ion is not executing (ry/by# pin is 1 ), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to ac characteristics on page 36 for reset# parameters and to figure 15.2 on page 37 for the timing diagram. 7.8 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins are placed in the high impedance state. note address range is a18:a-1 in byte mode and a18:a0 in word mode. see word/byte configuration on page 14 . table 7.2 s29al008d top boot block sector addresses sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) (x8) address range (x16) address range sa0 0 0 0 0 x x x 64/32 00000h?0ffffh 00000h?07fffh sa1 0 0 0 1 x x x 64/32 10000h?1ffffh 08000h?0ffffh sa2 0 0 1 0 x x x 64/32 20000h?2ffffh 10000h?17fffh sa3 0 0 1 1 x x x 64/32 30000h?3ffffh 18000h?1ffffh sa4 0 1 0 0 x x x 64/32 40000h?4ffffh 20000h?27fffh sa5 0 1 0 1 x x x 64/32 50000h?5ffffh 28000h?2ffffh sa6 0 1 1 0 x x x 64/32 60000h?6ffffh 30000h?37fffh sa7 0 1 1 1 x x x 64/32 70000h?7ffffh 38000h?3ffffh sa8 1 0 0 0 x x x 64/32 80000h?8ffffh 40000h?47fffh sa9 1 0 0 1 x x x 64/32 90000h?9ffffh 48000h?4ffffh sa10 1 0 1 0 x x x 64/32 a0000h?affffh 50000h?57fffh sa11 1 0 1 1 x x x 64/32 b0000h?bffffh 58000h?5ffffh sa12 1 1 0 0 x x x 64/32 c0000h?cffffh 60000h?67fffh sa13 1 1 0 1 x x x 64/32 d0000h?dffffh 68000h?6ffffh sa14 1 1 1 0 x x x 64/32 e0000h?effffh 70000h?77fffh sa15 1 1 1 1 0 x x 32/16 f0000h?f7fffh 78000h?7bfffh sa161111100 8/4 f80 00h?f9fffh 7c000h?7cfffh sa171111101 8/4 fa00 0h?fbfffh 7d000h?7dfffh sa18111111x 16/8 fc000h? fffffh 7e000h?7ffffh
february 27, 2009 s29al008d_00_a11 s29al008d 17 data sheet note address range is a18:a-1 in byte mode and a18:a0 in word mode. see word/byte configuration on page 14 . table 7.3 s29al008d bottom boot block sector addresses sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) (x8) address range (x16) address range sa0000000x 16/8 000 00h?03fffh 00000h?01fffh sa10000010 8/4 040 00h?05fffh 02000h?02fffh sa20000011 8/4 060 00h?07fffh 03000h?03fffh sa3 0 0 0 0 1 x x 32/16 08000h?0ffffh 04000h?07fffh sa4 0 0 0 1 x x x 64/32 10000h?1ffffh 08000h?0ffffh sa5 0 0 1 0 x x x 64/32 20000h?2ffffh 10000h?17fffh sa6 0 0 1 1 x x x 64/32 30000h?3ffffh 18000h?1ffffh sa7 0 1 0 0 x x x 64/32 40000h?4ffffh 20000h?27fffh sa8 0 1 0 1 x x x 64/32 50000h?5ffffh 28000h?2ffffh sa9 0 1 1 0 x x x 64/32 60000h?6ffffh 30000h?37fffh sa10 0 1 1 1 x x x 64/32 70000h?7ffffh 38000h?3ffffh sa11 1 0 0 0 x x x 64/32 80000h?8ffffh 40000h?47fffh sa12 1 0 0 1 x x x 64/32 90000h?9ffffh 48000h?4ffffh sa13 1 0 1 0 x x x 64/32 a0000h?affffh 50000h?57fffh sa14 1 0 1 1 x x x 64/32 b0000h?bffffh 58000h?5ffffh sa15 1 1 0 0 x x x 64/32 c0000h?cffffh 60000h?67fffh sa16 1 1 0 1 x x x 64/32 d0000h?dffffh 68000h?6ffffh sa17 1 1 1 0 x x x 64/32 e0000h?effffh 70000h?77fffh sa18 1 1 1 1 x x x 64/32 f0000h?fffffh 78000h?7ffffh
18 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 7.9 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 7.4 . in addition, when verifying sector protection, the sector address must appear on the appropr iate highest order address bits (see table 7.2 on page 16 and table 7.3 on page 17 ). table 7.4 shows the remaining address bits that are don?t care. when all necessary bits are set as required, the progr amming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 8.1 on page 26 . this method does not require v id . see command definitions on page 21 for details on using the autoselect mode. legend l = logic low = v il h = logic high = v ih sa = sector address x = don?t care. 7.10 sector protection/unprotection the hardware sector protection feature disables bot h program and erase operations in any sector. the hardware sector unprotection featur e re-enables both program and erase ope rations in previously protected sectors. the device is shipped with all sectors unprotected. sp ansion offers the option of programming and protecting sectors at its factory prior to shipping the device th rough spansion?s expressflash? service. contact an spansion representative for details. it is possible to determine whether a se ctor is protected or unprotected. see autoselect mode on page 18 for details. sector protection/unprotection ca n be implemented via two methods. the primary method requires v id on the reset# pin only, and can be im plemented either in-system or via programming equipment. figure 7.2 on page 20 shows the algorithms and figure 15.12 on page 43 shows the timing diagram. this method uses standard micr oprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected pr ior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines wr itten for earlier 3.0 volt-only spansion flash devices. publication number 20536 contains fu rther details; contact an spansion r epresentative to request a copy. table 7.4 s29al008d autoselect codes (high voltage method) description mode ce# oe# we# a18 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : spansion l l h x x v id xlxlll x 01h device id: s29al008d (top boot block) word l l h xxv id xlxllh 22h dah byte l l h xdah device id: s29al008d (bottom boot block) word l l h xxv id xlxllh 22h 5bh byte l l h x5bh sector protection verification l l h sa x v id xlxlhl x 01h (protected) x 00h (unprotected)
february 27, 2009 s29al008d_00_a11 s29al008d 19 data sheet 7.11 temporary sector unprotect this feature allows temporary unprotection of previo usly protected sectors to change data in-system. the sector unprotect mode is activate d by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pr otected sectors are protected again. figure 7.1 shows the algorithm, and figure 15.11 on page 42 shows the timing diagrams, for this feature. figure 7.1 temporary sector unprotect operation notes 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
20 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 7.2 in-system sector protect/se ctor unprotect algorithms s ector protect: write 60h to s ector a ddre ss with a6 = 0, a1 = 1, a0 = 0 s et u p s ector a ddre ss w a it 150 s verify s ector protect: write 40h to s ector a ddre ss with a6 = 0, a1 = 1, a0 = 0 re a d from s ector a ddre ss with a6 = 0, a1 = 1, a0 = 0 s ta rt pl s cnt = 1 re s et# = v id w a it 1 m s fir s t write cycle = 60h? d a t a = 01h? remove v id from re s et# write re s et comm a nd s ector protect complete ye s ye s no pl s cnt = 25? ye s device f a iled increment pl s cnt tempor a ry s ector unprotect mode no s ector unprotect: write 60h to s ector a ddre ss with a6 = 1, a1 = 1, a0 = 0 s et u p fir s t s ector a ddre ss w a it 15 m s verify s ector unprotect: write 40h to s ector a ddre ss with a6 = 1, a1 = 1, a0 = 0 re a d from s ector a ddre ss with a6 = 1, a1 = 1, a0 = 0 s ta rt pl s cnt = 1 re s et# = v id w a it 1 m s d a t a = 00h? l as t s ector verified? remove v id from re s et# write re s et comm a nd s ector unprotect complete ye s no pl s cnt = 1000? ye s device f a iled increment pl s cnt tempor a ry s ector unprotect mode no all s ector s protected? ye s protect a ll s ector s : the indic a ted portion of the s ector protect a lgorithm m us t b e performed for a ll u nprotected s ector s prior to i ssu ing the fir s t s ector u nprotect a ddre ss s et u p next s ector a ddre ss no ye s no ye s no no ye s no s ector protect algorithm s ector unprotect algorithm fir s t write cycle = 60h? protect a nother s ector? re s et pl s cnt = 1
february 27, 2009 s29al008d_00_a11 s29al008d 21 data sheet 7.12 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 8.1 on page 26 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or pr ogramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down tran sitions, or from system noise. 7.12.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 7.12.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 7.12.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 7.12.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is aut omatically reset to reading array data on power-up. 8. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 8.1 on page 26 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens firs t. refer to the appropriate timing diagrams in the ac characteristics on page 36 . 8.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command , the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase- suspended sectors, the device outpu ts status data. after completing a programming operation in the erase suspend mode, the system may once again r ead array data with the same exception. see erase suspend/ erase resume commands on page 25 for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see reset command on page 22 . see also requirements for reading array data on page 14 for more information. table 15.1, read operations on page 36 provides the read parameters, and figure 15.1 on page 36 shows the timing diagram.
22 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 8.2 reset command writing the reset command to the device resets the devic e to reading array data. address bits are don?t care for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the device to reading a rray data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the device to readi ng array data (also applies to programming in erase suspend mode). once programming begins, however, th e device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). 8.3 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 8.1 on page 26 shows the address and data requirements. this method is an alternative to that shown in table 7.4 on page 18 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mo de, and the system may read at any address any number of times, without initia ting another command sequence. a read cycle at address xx00h retrieves the manufact urer code. a read cycle at address xx01h in word mode (or 02h in byte mode) returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is prot ected, or 00h if it is unprotected. refer to table 7.2 on page 16 and table 7.3 on page 17 for valid sector addresses. the system must write the reset command to exit th e autoselect mode and return to reading array data. 8.4 word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequen ce is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generat ed program pulses and verifies the programmed cell margin. table 8.1 on page 26 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7, dq6, or ry/by#. see write operation status on page 27 for information on these status bits. any commands written to the device during the embe dded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1 , or cause the data# polling algorithm to indicate the operation was successful. howe ver, a succeeding read show s that the data is still 0 . only erase operations can convert a 0 to a 1.
february 27, 2009 s29al008d_00_a11 s29al008d 23 data sheet 8.5 unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device fast er than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command , 20h. the device then enters the unl ock bypass mode. a two-cycle unlock bypass progr am command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 8.1 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contai n the data 90h; the se cond cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. table 8.1 illustrates the algorithm fo r the program operation. see erase/program operations on page 39 for parameters, and figure 15.5 on page 39 for timing diagrams. figure 8.1 program operation note see table 8.1 on page 26 for program command sequence. s ta rt write progr a m comm a nd s e qu ence d a t a poll from s y s tem verify d a t a ? no ye s l as t addre ss ? no ye s progr a mming completed increment addre ss em b edded progr a m a lgorithm in progre ss
24 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 8.6 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 8.1 on page 26 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the em bedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately te rminates the operation. the chip erase command sequence should be reinitiated once the device retu rns to reading array data, to ensure data integrity. the system can determine th e status of the erase op eration by using dq7, dq6, dq2, or ry/by#. see write operation status on page 27 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 8.2 on page 25 illustrates the algorithm fo r the erase operation. see erase/program operations on page 39 for parameters, and figure 15.6 on page 40 for timing diagrams. 8.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up co mmand. two additional unlock write cycles are then followed by the address of the sector to be erased , and the sector erase command. table 8.1 on page 26 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memo ry prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands ma y be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, ot herwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additi onal sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the de vice to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see dq3: sector erase timer on page 30 .) the time-out begins from the rising ed ge of the final we# pulse in the command sequence. once the sector erase operation begins, only the eras e suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the st atus of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to write operation status on page 27 for information on these status bits. figure 8.2 on page 25 illustrates the algorithm for the erase operation. refer to erase/program operations on page 39 for parameters, and to figure 15.6 on page 40 for timing diagrams.
february 27, 2009 s29al008d_00_a11 s29al008d 25 data sheet 8.8 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for er asure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediatel y terminates the time-out period and suspends the erase operation. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediatel y terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the system can re ad array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status on page 27 for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the st atus of the program operation using the dq7 or dq6 status bits, just as in t he standard program operation. see write operation status on page 27 for more information. the system may also write the autoselect comma nd sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence on page 22 for more information. the system must write the erase resume command (address bits are don?t care ) to exit the erase suspend mode and continue the sector erase operation. furthe r writes of the resume command are ignored. another erase suspend command can be written after the device resumes erasing. figure 8.2 erase operation notes 1. see table 8.1 on page 26 for erase command sequence. 2. see dq3: sector erase timer on page 30 for more information. s ta rt write er as e comm a nd s e qu ence d a t a poll from s y s tem d a t a = ffh? no ye s er asu re completed em b edded er as e a lgorithm in progre ss
26 s29al008d s29al008d_00_a11 february 27, 2009 data sheet legend x = don?t care ra = address of the memory location to be read rd = data read from location ra during read operation, and pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18?a12 uniquely select any sector. notes 1. see table 7.1 on page 14 for a description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a18?a11 are don?t cares for unlock and command cycles, unless pa or sa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data w hen device is in the autoselect mode, or if dq5 goes high (whi le the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see autoselect command sequence on page 22 for more information. 10. the unlock bypass command is required pr ior to the unlock bypass program command. 11. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation. 13. the erase resume command is valid only during the erase suspend mode. table 8.1 s29al008d command definitions command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id, top boot block word 4 555 aa 2aa 55 555 90 x01 22da byte aaa 555 aaa x02 da device id, bottom boot block word 4 555 aa 2aa 55 555 90 x01 225b byte aaa 555 aaa x02 5b sector protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 byte aaa 555 aaa (sa) x04 00 01 program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 (f0) chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30
february 27, 2009 s29al008d_00_a11 s29al008d 27 data sheet 9. write operation status the device provides several bits to determine the stat us of a write operation: dq 2, dq3, dq5, dq6, dq7, and ry/by#. table 9.1 on page 31 and the following subsections descri be the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. 9.1 dq7: data# polling the data# polling bit, dq7, indicates to the host sys tem whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for appro ximately 1 s, then the device returns to reading array data. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete , or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum out put described for the embed ded program algorithm: the erase function changes all the bits in a sector to 1 ; prior to this, the device outputs the complement , or 0 . the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the devic e returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. when the system detects dq7 changes from the complement to true data, it can read valid data at dq7?dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 15.8, data# polling timings (during embedded algorithms) on page 41 , illustrates this. table 9.1 on page 31 shows the outputs for data# polling on dq7. figure 9.1 on page 28 shows the data# polling algorithm.
28 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 9.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 9.2 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin th at indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 9.1 on page 31 shows the outputs for ry/by#. figure 15.1 on page 36 , figure 15.2 on page 37 , figure 15.5 on page 39 and figure 15.6 on page 40 shows ry/by# for read, reset, program, and erase operations, respectively. 9.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device entered the er ase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. dq7 = d a t a ? ye s no no dq5 = 1? no ye s ye s fail pa ss re a d dq7?dq0 addr = va re a d dq7?dq0 addr = va dq7 = d a t a ? s ta rt
february 27, 2009 s29al008d_00_a11 s29al008d 29 data sheet during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see dq7: data# polling on page 27 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 9.1 on page 31 shows the outputs for toggle bit i on dq6. figure 9.2 on page 30 shows the toggle bit algorithm. figure 15.9 on page 41 shows the toggle bit timing diagrams. figure 15.10 on page 42 shows the differences between dq2 and dq6 in graphical form. see also dq2: toggle bit ii on page 29 . 9.4 dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that were selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase su spend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 9.1 on page 31 to compare outputs for dq2 and dq6. figure 9.2 on page 30 shows the toggle bit algorithm in flowchart form, and dq2: toggle bit ii on page 29 explains the algorithm. see also dq6: toggle bit i on page 28 . figure 15.9 on page 41 shows the toggle bit timing diagram. figure 15.10 on page 42 shows the differences between dq2 and dq6 in graphical form. 9.5 reading toggle bits dq6/dq2 refer to figure 9.2 on page 30 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the t oggle bit is not toggling, the device completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whether the value of dq5 is high (see dq5: exceeded timing limits on page 30 ). if it is, the system should then determine again whet her the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the program or erase operation. if it is st ill toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 9.2 on page 30 ).
30 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 9.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure conditi on may appear if the syst em tries to program a 1 to a location that is previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and when the operation e xceeds the timing limits, dq5 produces a 1 . under both these conditions, the system must issue the reset command to re turn the device to reading array data. 9.7 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whet her or not an erase operation started. (t he sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, t he entire time-out also applies after each additional sector erase command. when the time-out is comp lete, dq3 switches from 0 to 1 . the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands is always less than 50 s. see also sector erase command sequence on page 24 . figure 9.2 toggle bit algorithm notes 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. s ta rt no ye s ye s dq5 = 1? no ye s toggle bit = toggle? no progr a m/er as e oper a tion not complete, write re s et comm a nd progr a m/er as e oper a tion complete re a d dq7?dq0 toggle bit = toggle? re a d dq7?dq0 tw i c e re a d dq7?dq0 (notes 1, 2) (note 1)
february 27, 2009 s29al008d_00_a11 s29al008d 31 data sheet after the sector erase command sequ ence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device accepted the command sequenc e, and then read dq3. if dq3 is 1 , the internally controlled erase cycle started; al l further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts add itional sector erase commands. to ensure the command is accepted, the syst em software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not be accepted. table 9.1 shows the outputs for dq3. notes 1. dq5 switches to 1 when an embedded program or embedded erase operation exceeds the maximum timing limits. see dq5: exceeded timing limits on page 30 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 10. absolute maximum ratings notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 on page 32 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/ o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11.2 on page 32 . 2. minimum dc input voltage on pins a9, oe#, and reset# is ?0.5 v. during voltage transitions, a9, oe#, and reset# may undershoo t v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 on page 32 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. table 9.1 write operation status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 parameter rating storage temperature plastic packages ?65 c to +150 c ambient temperature with power applied ?65 c to +125 c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) ?0.5 v to +12.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma
32 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 11. operating ranges industrial (i) devices ambient temperature (t a ) -40c to +85c extended (n) devices ambient temperature (t a ) -40c to +125c v cc supply voltages v cc for regulated voltage range+3.0 v to +3.6 v v cc for full voltage range +2.7 v to +3.6 v operating ranges define those limits between wh ich the functionality of the device is guaranteed figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform 20 ns 20 ns 20 ns +0.8 v ?0.5 v ?2.0 v 20 ns 20 ns 20 ns v cc +2.0 v v cc +0.5 v 2.0 v
february 27, 2009 s29al008d_00_a11 s29al008d 33 data sheet 12. dc characteristics notes 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v ccmax . 3. i cc active while embedded erase or embedded program is in progress. 4. at extended temperature range (>+85c), typical current is 5a and maximum current is 10a. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il, oe# = v ih, byte mode 10 mhz 15 30 ma 5 mhz 9 16 1 mhz 2 4 ce# = v il, oe# = v ih, word mode 10 mhz 15 30 5 mhz 9 16 1 mhz 2 4 i cc2 v cc active write current (notes 2 , 3 , 6 ) ce# = v il, oe# = v ih 20 35 ma i cc3 v cc standby current (notes 2 , 4 ) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (notes 2 , 4 ) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 , 5 ) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 2.4 v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage 2.3 2.5 v
34 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 12.1 zero power flash figure 12.1 i cc1 current vs. time (showing active and automatic sleep currents) note addresses are switching at 1 mhz figure 12.2 typical i cc1 vs. frequency note t = 25 c 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma 2.7 v 3.6 v 4 6
february 27, 2009 s29al008d_00_a11 s29al008d 35 data sheet 13. test conditions figure 13.1 test setup note nodes are in3064 or equivalent. 14. key to switching waveforms figure 14.1 input waveforms and measurement levels table 13.1 test specifications test condition 55 60 70 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 30 30 100 pf input rise and fall times 5ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc output timing measurement reference levels 0.5 v cc 2.7 k c l 6.2 k 3.3 v device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v output measurement level input 0.5 v cc 0.5 v cc
36 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 15. ac characteristics notes 1. not 100% tested. 2. see figure 13.1 on page 35 and dc characteristics on page 33 for test specifications. figure 15.1 read operations timings table 15.1 read operations parameter description speed options jedec std test setup 55 60 70 90 unit t avav t rc read cycle time (note 1) min 55 60 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 55 60 70 90 t elqv t ce chip enable to output delay oe# = v il max 55 60 70 90 t glqv t oe output enable to output delay max 25 25 30 35 t ehqz t df chip enable to output high z (note 1) max 16 t ghqz t df output enable to output high z (note 1) max 16 t sr/w latency between read and write operations min 20 t oeh output enable hold time (note 1) read min 0 toggle and data# polling min 10 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t sr/w t oh
february 27, 2009 s29al008d_00_a11 s29al008d 37 data sheet note not 100% tested. figure 15.2 reset# timings table 15.2 hardware reset (reset#) parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) 500 ns t rp reset# pulse width min 500 t rh reset# high time before read (see note) 50 t rpd reset# low to standby mode 20 s t rb ry/by# recovery time 0 ns re s et# ry/by# ry/by# t rp t re a dy re s et timing s not d u ring em b edded algorithm s t re a dy ce#, oe# t rh ce#, oe# re s et timing s d u ring em b edded algorithm s re s et# t rp t rb
38 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 15.3 byte# timings for read operations figure 15.4 byte# timings for write operations note refer to erase/program operations on page 39 for t as and t ah specifications. table 15.3 word/byte configuration (byte#) parameter description speed options jedec std 55 60 70 90 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 t fhqv byte# switching high to output active min 55 60 70 90 dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
february 27, 2009 s29al008d_00_a11 s29al008d 39 data sheet 15.1 erase/program operations notes 1. not 100% tested. 2. see erase and programming performance on page 44 for more information. figure 15.5 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode parameter description speed options jedec std 55 60 70 90 unit t avav t wc write cycle time (note 1) min 55 60 70 90 ns t avwl t as address setup time 0 t wlax t ah address hold time 45 t dvwh t ds data setup time 35 35 35 45 t whdx t dh data hold time 0 t oes output enable setup time 0 t ghwl t ghwl read recovery time before write (oe# high to we# low) 0 t elwl t cs ce# setup time 0 t wheh t ch ce# hold time 0 t wlwh t wp write pulse width 35 t whwl t wph write pulse width high 30 t sr/w latency between read and write operations 20 ns t whwh1 t whwh1 programming operation (note 2) byte ty p 7 s word 7 t whwh2 t whwh2 sector erase operation (note 2) 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 oe# we# ce# v cc d a t a addre ss e s t d s t ah t d t wp pd t whwh1 t wc t a s t wph t vc s 555h pa pa re a d s t a t us d a t a (l as t two cycle s ) a0h t c s s t a t us d out progr a m comm a nd s e qu ence (l as t two cycle s ) ry/by# t rb t bu s y t ch pa
40 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 15.6 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 27 ). 2. illustration shows de vice in word mode. figure 15.7 back to back read/write cycle timing oe# ce# addre ss e s v cc we# d a t a 2aah s a t ah t wp t wc t a s t wph 555h for chip er as e 10 for chip er as e 3 0h t d s t vc s t c s t dh 55h t ch in progre ss complete t whwh2 va va er as e comm a nd s e qu ence (l as t two cycle s )re a d s t a t us d a t a ry/by# t rb t bu s y pa v a lid in v a lid in v a lid o u t v a lid o u t pa pa ra t wc t ah t wp t d s t oh t dh t df t ce t cp t oe t rc t acc t wdh t cph t ghwl t s r/w addre ss e s d a t a we# oe# ce#
february 27, 2009 s29al008d_00_a11 s29al008d 41 data sheet figure 15.8 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle figure 15.9 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t bu s complement tr u e addre ss e s va t oeh t ce t ch t oh t df va va s t a t us d a t a complement s t a t us d a t a tr u e v a lid d a t a v a lid d a t a t acc t rc we# ce# oe# high z t oe dq6/dq2 ry/by# t bu s addre ss e s va t oeh t ce t ch t oh t df va va t acc t rc v a lid d a t a v a lid s t a t us v a lid s t a t us (fir s t re a d) ( s econd re a d) ( s top s toggling) v a lid s t a t us va
42 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 15.10 dq2 vs. dq6 note the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. note not 100% tested. figure 15.11 temporary sector unprotect timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing table 15.4 temporary sector unprotect parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s re s et# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t r s p progr a m or er as e comm a nd s e qu ence 0 or 3 v
february 27, 2009 s29al008d_00_a11 s29al008d 43 data sheet figure 15.12 sector protect/unpr otect timing diagram note for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. notes 1. not 100% tested. 2. see erase and programming performance on page 44 for more information. table 15.5 alternate ce# controlled erase/program operations parameter speed options jedec std description 55 60 70 90 unit t avav t wc write cycle time (note 1) min 55 60 70 90 ns t avel t as address setup time 0 t elax t ah address hold time 45 t dveh t ds data setup time 35 35 35 45 t ehdx t dh data hold time 0 t oes output enable setup time 0 t ghel t ghel read recovery time before write (oe# high to we# low) 0 t wlel t ws we# setup time 0 t ehwh t wh we# hold time 0 t eleh t cp ce# pulse width 35 t ehel t cph ce# pulse width high 30 t sr/w latency between read and write operations 20 ns t whwh1 t whwh1 programming operation (note 2) byte ty p 7 s word 7 t whwh2 t whwh2 sector erase operation (note 2) 0.7 sec s ector protect: 150 s s ector unprot ect: 15 m s 1 s re s et# s a, a6, a1, a0 d a t a ce# we# oe# 60h 60h 40h v a lid* v a lid* v a lid* s t a t us s ector protect/unprotect verify v id v ih
44 s29al008d s29al008d_00_a11 february 27, 2009 data sheet figure 15.13 alternate ce# controlled write operation timings notes 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last tw o bus cycles of command sequence. 3. word mode address used as an example. 15.2 erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 8.1 on page 26 for further information on command definitions. 6. the device has a guaranteed minimum eras e and program cycle endurance of 1,000,000 cycles. t ghel t w s oe# ce# we# re s et# t d s d a t a t ah addre ss e s t dh t cp dq7# d out t wc t a s t cph pa d a t a # polling a0 for progr a m 55 for er as e t rh t whwh1 or 2 ry/by# t wh pd for progr a m 3 0 for s ector er as e 10 for chip er as e 555 for progr a m 2aa for er as e pa for progr a m s a for s ector er as e 555 for chip er as e t bu s y parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 10 s excludes 00h programming prior to erasure chip erase time 14 s byte programming time 7 210 s excludes system level overhead (note 5) word programming time 7 210 s chip programming time (note 3) byte mode 8.4 25 s word mode 5.8 17 s
february 27, 2009 s29al008d_00_a11 s29al008d 45 data sheet note includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 15.6 latchup characteristics description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma table 15.7 tsop, so, and bga pin capacitance parameter symbol parameter description test setup package typ max unit c in input capacitance v in = 0 tsop, so 6 7.5 pf bga 4.2 5.0 c out output capacitance v out = 0 tsop, so 8.5 12 bga 5.4 6.5 c in2 control pin capacitance v in = 0 tsop, so 7.5 9 bga 3.9 4.7
46 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 16. physical dimensions 16.1 ts 048?48-pin standard tsop note for reference only. bsc is an ansi standard for basic space centering. 3 641 \ 16-0 38 .10 \ 7.10.7 package t s /t s r 4 8 jedec mo-142 (b) dd s ymbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0. 9 5 1.00 1.05 b 1 0.17 0.20 0.2 3 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d1 9 . 8 0 20.00 20.20 d1 1 8 . 3 01 8 .40 1 8 .50 e 11. 9 0 12.00 12.10 e 0.50 ba s ic l 0.50 0.60 0.70 0? --- 8 r 0.0 8 --- 0.20 n4 8 note s : 1. controlling dimen s ion s are in millimeter s (mm). (dimen s ioning and tolerancing conform to an s i y14.5m-1 98 2) 2. pin 1 identifier for s tandard pin out (die up). 3 . pin 1 identifier for rever s e pin out (die down): ink or la s er mark. 4. to be determined at the s eating plane -c- . the s eating plane i s defined a s the plane of contact that i s made when the package lead s are allowed to re s t freely on a flat horizontal s urface. 5. dimen s ion s d1 and e do not include mold protru s ion. allowable mold protu s ion i s 0.15mm (.005 9 ") per s ide. 6. dimen s ion b doe s not include dambar protu s ion. allowable dambar protu s ion s hall be 0.0 8 mm (0.00 3 1") total in exce ss of b dimen s ion at max. material condition. minimum s pace between protru s ion and an adjacent lead to be 0.07mm (0.002 8 "). 7. the s e dimen s ion s apply to the flat s ection of the lead between 0.10mm (.00 39 ") and 0.25mm (0.00 98 ") from the lead tip. 8 . lead coplanarity s hall be within 0.10mm (0.004") a s mea s ured from the s eating plane. 9 . dimen s ion "e" i s mea s ured at the centerline of the lead s .
february 27, 2009 s29al008d_00_a11 s29al008d 47 data sheet 16.2 vbk 048?48 ball fine-pitch ba ll grid array (fbga) 8.15 x 6.15 mm 3338 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbk 048 jedec n/a 6.15 mm x 8.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count fb 0.35 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m f 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h fb e1 d1 c f 0.08 pin a1 corner index mark
48 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 16.3 so 044?44-pin small outline package dwg rev ac; 10/99
february 27, 2009 s29al008d_00_a11 s29al008d 49 data sheet 17. revision history 17.1 revision a (september 8, 2004) initial release 17.2 revision a 1 (february 18, 2005) global updated trademark ordering information added package type designator valid combinations changed package type, material, and temperature range designator under package description s, change ssop to sop 17.3 revision a2 (june 1, 2005) global updated status from advance info rmation to preliminary data sheet. distinctive characteristics updated manufactured process technology. updat ed high performance access time. added extended temperature range. added cyc ling endurance information. production selector guide added 55 ns speed option and column. ordering information added tube and tray packing types. added extended temperature range added model numbers. valid combinations table added speed option. added packing types. added model number. added note for this table. operating range added extended temperature range information. test conditions added 55ns speed option. ac characteristics read operation table: added 55ns speed option. word/byte config uration table: added 55 ns speed option. erase/program operation table: added 55ns speed option. alternate ce# controlled eras e/program operation table: added 55 ns speed option. erase and programming performance: changed byte programing time values for typical and maximum.
50 s29al008d s29al008d_00_a11 february 27, 2009 data sheet 17.4 revision a3 (june 16, 2005) changed from preliminary to full data sheet. updated valid combinations table. 17.5 revision a4 (february 16, 2006) corrected minor typo on page 1. added cover page. 17.6 revision a5 (may 22, 2006) ac characteristics added t sr/w parameter to read and erase/ program operations tables. a dded back-to-back read/write cycle timing diagram. changed maximum value for t df and t flqz . 17.7 revision a6 (september 6, 2006) global added 60 ns speed option. 17.8 revision a7 (october 31, 2006) automatic sleep mode changed i cc4 to i cc5 in description. ac characteristics, erase / program operations changed t busy to a maximum value. 17.9 revision a8 (august 29, 2007) ts048 physical dimensions changed revision from aa to e: changed degrees (max) from 5 to 8 17.10 revision a9 (september 19, 2007) product selector guide changed toe for 55ns access speed autoselect codes table changed part references to al008d added a3 to a2 column command definitions table added f0 as an alternat ive 2nd cycle command fo r unlock bypass reset test specifications table added cl = 30 pf under 60 ns access speed changed input pulse levels, input and outp ut timing measurement reference levels erase/program operations table changed value of programming operation for byte mode alternate ce# controlled erase/program operations table changed values of program operation for both byte & word modes changed value of sector erase operation
february 27, 2009 s29al008d_00_a11 s29al008d 51 data sheet 17.11 revision a10 (november 27, 2007) figure: input waveforms and measurement levels updated figure 17.12 revision a11 (february 27, 2009) global added obsolescence information to cover sheet, distinctive characteri stics, and ordering information sections of data sheet.
52 s29al008d s29al008d_00_a11 february 27, 2009 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2009 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , ornand2 ? , hd-sim ? , ecoram ? and combinations thereof, are tradem arks of spansion llc in the us and other countries. other names used are for informational purposes only and ma y be trademarks of their respective owners.

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